The single-chip microcomputer comprises a CPU and a plurality of peripheral circuits, which are constructed on the same chip as the CPU. As the number of processing functions to be executed by the single-chip microcomputer increases, the number of peripheral circuits incorporated in the chip needs to be raised as well. In addition, the peripheral circuits incorporated in the chip also vary in dependence on the application of the single-chip microcomputer.
In development using the single-chip microcomputer, an emulation apparatus is used for emulating functions of the microcomputer. In order to keep up with increases in peripheral-circuit count and variations of the peripheral circuits with a high degree of flexibility, the emulation apparatus is in some cases designed into a multi-chip configuration comprising different semiconductor chips serving as a portion for emulating functions of the CPU and a portion for emulating functions of the peripheral circuits. Japanese Patent Laid-open No. Hei5-334460 referred to hereafter as patent reference 1 discloses a typical configuration of such an emulation apparatus.
If the multi-chip emulation apparatus for emulating functions of a single-chip microcomputer 1 is designed into a multi-chip configuration, however, a problem like one described below is raised. Assume that the single-chip microcomputer 1 comprises a CPU 2, a peripheral circuit 3, and an interrupt control circuit 4 as shown in FIG. 5. In the single-chip microcomputer 1, the peripheral circuit 3 makes a request for an interrupt and supplies the request to the interrupt control circuit 4 with a timing in a clock cycle (1) of timing charts shown in FIG. 6B. In this case, the interrupt control circuit 4 outputs a selected interrupt-request signal INT to the CPU 2 with a timing at the beginning of a clock cycle (3) as shown in FIG. 6C. As shown in the timing charts of FIGS. 6A to 6D, the timing to output the selected interrupt-request signal INT to the CPU 2 lags behind the timing to supply the request for an interrupt to the interrupt control circuit 4 by about 1 clock cycle. Then, the CPU 2 starts an interrupt-handling process at the beginning of a clock cycle (4) as shown in FIG. 6D.
Assume a case in which a multi-chip emulation apparatus 5 for emulating this single-chip microcomputer 1 has a configuration shown in FIG. 7. As shown in the figure, the multi-chip emulation apparatus 5 comprises a CPU 6, a peripheral-circuit chip 7 and an interrupt-controller chip 8, which are constructed as chips independent of each other. These chips for the CPU 6, the peripheral-circuit chip 7, and the interrupt-controller chip 8 respectively emulate functions of the CPU 2, the peripheral circuit 3, and the interrupt control circuit 4, which are employed in the single-chip microcomputer 1.
Let the multi-chip emulation apparatus 5 emulate a state in which the peripheral circuit 3 makes a request for an interrupt and supplies the request to the interrupt control circuit 4 with a timing in a clock cycle (1) as indicated by a dashed line in timing charts shown in FIG. 8B. However, the peripheral-circuit chip 7 supplies the request to the interrupt-controller chip 8 with a timing in a clock cycle (2) as indicated by a solid line in timing charts shown in FIG. 8B. The timing indicated by the solid line lags behind the timing indicated by the dashed line by a time delay caused by a wire between the chip of the peripheral-circuit chip 7 and the chip of the interrupt-controller chip 8.
In this case, since the interrupt-controller chip 8 recognizes the request for an interrupt in a clock cycle (3), the interrupt-controller chip 8 outputs a selected interrupt-request signal INT to the CPU 6 with a timing in a clock cycle (4) as shown in FIG. 8C. As a result, the CPU 6 starts interrupt-handling at a clock cycle (5) as shown in FIG. 8D. These timings shown in FIGS. 8A to 8D for the multi-chip emulation apparatus 5 are different from those shown in FIGS. 6A to 6D for the single-chip microcomputer 1 without such a time delay.
Accordingly, the interrupt-handling timing in the multi-chip emulation apparatus 5 is not compatible with the interrupt-handling timing, with which the single-chip microcomputer 1 actually operates, resulting in fear of disagreement between the processing timing recognized by the emulation and the timing with which the single-chip microcomputer 1 actually carries out the processing.